College of Information Technology

Research output

Research output per year 1982 2019 2020 2021 2022 2023 2024 2024

• 33473 Citations
• 76 h-index
• 1138 Conference contribution
• 839 Article
• 89 Review article
• 81 Chapter
• 131 More
  • 44 Conference article
  • 30 Editorial
  • 14 Comment/debate
  • 13 Book
  • 13 Patent
  • 9 Paper
  • 4 Foreword/postscript
  • 1 Chapter (peer-reviewed)
  • 1 Short survey
  • 1 Other contribution
  • 1 Preprint

Research output per year

Research output per year

Search results

• 2003

  Low-Power Differential Conductance-Based Logic Gate and Method of Operation Thereof

  Beiu, V. (Inventor), Jun 17 2003, Patent No. US 6,580,296

  Research output: Patent

• Microprocessor and a Digital Signal Processor Including Adder and Multiplier Circuits Employing Logic Gates Having Discrete and Weighted Inputs

  Beiu, V. (Inventor), Feb 4 2003, Patent No. US 6,516,331

  Research output: Patent
• 2002

  Adder and Multiplier Circuits Employing Logic Gates Having Discrete, Weighted Inputs and Methods of Performing Combinatorial Operations Therewith

  Beiu, V. (Inventor), Apr 1 2002, Patent No. TW 481774

  Research output: Patent

• Adder Circuits Employing Logic Gates Having Discrete Weighted Inputs and a Method of Operation Therewith

  Beiu, V. (Inventor), Dec 31 2002, Patent No. US 6,502,120

  Research output: Patent

• Adder Having Reduced Number of Internal Layers and Method of Operation Thereof

  Beiu, V. (Inventor), Aug 20 2002, Patent No. US 6,438,572

  Research output: Patent

• Adder Having Reduced Number of Internal Layers and Method of Operation Thereof

  Beiu, V. (Inventor), Jul 1 2002, Patent No. TW 493139

  Research output: Patent

• Noise Tolerant Conductance-Based Logic Gate and Methods of Operation and Manufacturing Thereof

  Beiu, V. (Inventor), Aug 6 2002, Patent No. US 6,430,585

  Research output: Patent

• Noise Tolerant Conductance-Based Logic Gate and Methods of Operation and Manufacturing Thereof

  Beiu, V. (Inventor), Apr 11 2002, Patent No. TW 483249

  Research output: Patent
• 2001

  Adder and Multiplier Circuits Employing Logic Gates Having Discrete, Weighted Inputs and Methods of Performing Combinatorial Operations Therewith

  Beiu, V. (Inventor), Mar 20 2001, Patent No. US 6,205,458

  Research output: Patent

• Logic Gate Having Reduced Power Dissipation and Method of Operation Thereof

  Beiu, V. (Inventor), Jul 10 2001, Patent No. US 6,259,275

  Research output: Patent
• 1984

  LSI Unit for Mutual Exclusion

  Beiu, V. (Inventor), Apr 26 1984, Patent No. RO 84763

  Research output: Patent
• 1800

  Method and system for de-jittering of transmitted MPEG-2 and MPEG-4 video

  Basch, E. (Inventor), Shuaib, K. (Inventor), Saadawi, T. (Inventor), Gringeri, S. (Inventor) & Lee, M. (Inventor), 1800, Patent No. 7,012,982

  Research output: Patent

• System and method for analyzing and transmitting video over a switched network

  Gringeri, S. (Inventor), Shuaib, K. (Inventor) & Basch, E. (Inventor), 1800, Patent No. 6,233,226

  Research output: Patent