10Gbit/s 2mW inductorless transimpedance amplifier

Mohamed Atef, Horst Zimmermann

Research output: Contribution to conferencePaperpeer-review

23 Citations (Scopus)

Abstract

This work presents the design and performance of a 10Gbit/s transimpedance amplifier (TIA) implemented in a 40nm CMOS technology. The introduced TIA uses an inverter with active common-drain feedback (ICDF-TIA). The TIA is followed by a two-stage differential amplifier and a 50 differential output driver to provide an interface to the measurement setup. The optical receiver shows an optical sensitivity of 19dBm for a BER= 10 12. The transimpedance amplifier achieves a transimpedance gain of 47dB, 8GHz bandwidth with 0.45pF total input capacitance for the photodiode, ESD protection and input PAD. The TIA occupies 0.0002mm 2 whereas the complete optical receiver occupies a chip area of 0.16mm 2. The power consumption of the TIA is only 2mW and the complete chip dissipates 16mW for a 1.1V single supply voltage. The complete optical receiver has a 58dB transimpedance gain and 7GHz bandwidth.

Original languageEnglish
Pages1728-1731
Number of pages4
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: May 20 2012May 23 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/TerritoryKorea, Republic of
CitySeoul
Period5/20/125/23/12

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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