TY - GEN
T1 - 10Gb/s inverter based cascode transimpedance amplifier in 40nm CMOS technology
AU - Atef, Mohamed
AU - Chen, Hong
AU - Zimmermann, Horst
PY - 2013
Y1 - 2013
N2 - This work presents the design and performance of a 10Gbit/s transimpedance amplifier (TIA) implemented in a 40nm CMOS technology. The introduced TIA uses an inverter based cascode feedback (Inv-Cascode-TIA) with shunt feedback resistor. The TIA is followed by an one-stage single-ended common-source amplifier (CS), a two-stage differential amplifier and a 50o differential output driver to provide an interface to the measurement setup. The optical receiver shows an optical sensitivity of -21.4dBm for a BER= 10-12. The transimpedance amplifier achieves a transimpedance gain of 55.3dBo, 8GHz bandwidth with 0.45pF total input capacitance. The power consumption of the TIA is 3.01mW and the complete chip dissipates 19.25mW for a 1.2V single supply voltage. The complete optical receiver has a 69.2dBo transimpedance gain and 7GHz bandwidth.
AB - This work presents the design and performance of a 10Gbit/s transimpedance amplifier (TIA) implemented in a 40nm CMOS technology. The introduced TIA uses an inverter based cascode feedback (Inv-Cascode-TIA) with shunt feedback resistor. The TIA is followed by an one-stage single-ended common-source amplifier (CS), a two-stage differential amplifier and a 50o differential output driver to provide an interface to the measurement setup. The optical receiver shows an optical sensitivity of -21.4dBm for a BER= 10-12. The transimpedance amplifier achieves a transimpedance gain of 55.3dBo, 8GHz bandwidth with 0.45pF total input capacitance. The power consumption of the TIA is 3.01mW and the complete chip dissipates 19.25mW for a 1.2V single supply voltage. The complete optical receiver has a 69.2dBo transimpedance gain and 7GHz bandwidth.
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U2 - 10.1109/DDECS.2013.6549791
DO - 10.1109/DDECS.2013.6549791
M3 - Conference contribution
AN - SCOPUS:84881336460
SN - 9781467361361
T3 - Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013
SP - 72
EP - 75
BT - Proceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013
PB - IEEE Computer Society
T2 - 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013
Y2 - 8 April 2013 through 10 April 2013
ER -