2.5Gbit/s transimpedance amplifier using noise cancelling for optical receivers

Mohamed Atef; Horst Zimmermann

doi:10.1109/ISCAS.2012.6271599

2.5Gbit/s transimpedance amplifier using noise cancelling for optical receivers

Mohamed Atef, Horst Zimmermann

Research output: Contribution to conference › Paper › peer-review

23 Citations (Scopus)

Abstract

This work presents the design and performance of a 2.5Gbit/s transimpedance amplifier (TIA) for optical receivers implemented in a 40nm CMOS technology. The TIA is based on an inverting voltage amplifier with a shunt feedback resistor using noise cancelling technique to reduce the input noise. The TIA is followed by two stages of differential limiting amplifiers and the last stage is a 50 differential output driver to provide an interface to the measurement setup. The TIA shows a post layout simulated optical sensitivity of 25dBm for a BER= 10 ¹² and an optical power dynamic range of 25dB. The complete chip achieves a transimpedance gain of 79.5dB, 1.5GHz bandwidth and occupies a chip area of 0.16mm ². The power consumption of the TIA is only 4.5mW and the complete chip dissipates 15mW for a 1.1V single supply voltage.

Original language	English
Pages	1740-1743
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271599
Publication status	Published - 2012
Externally published	Yes
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: May 20 2012 → May 23 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	5/20/12 → 5/23/12

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2012.6271599

Cite this

@conference{9e8179aa006a4fb48510acba77cf1fc9,

title = "2.5Gbit/s transimpedance amplifier using noise cancelling for optical receivers",

abstract = "This work presents the design and performance of a 2.5Gbit/s transimpedance amplifier (TIA) for optical receivers implemented in a 40nm CMOS technology. The TIA is based on an inverting voltage amplifier with a shunt feedback resistor using noise cancelling technique to reduce the input noise. The TIA is followed by two stages of differential limiting amplifiers and the last stage is a 50 differential output driver to provide an interface to the measurement setup. The TIA shows a post layout simulated optical sensitivity of 25dBm for a BER= 10 12 and an optical power dynamic range of 25dB. The complete chip achieves a transimpedance gain of 79.5dB, 1.5GHz bandwidth and occupies a chip area of 0.16mm 2. The power consumption of the TIA is only 4.5mW and the complete chip dissipates 15mW for a 1.1V single supply voltage.",

author = "Mohamed Atef and Horst Zimmermann",

year = "2012",

doi = "10.1109/ISCAS.2012.6271599",

language = "English",

pages = "1740--1743",

note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

}

TY - CONF

T1 - 2.5Gbit/s transimpedance amplifier using noise cancelling for optical receivers

AU - Atef, Mohamed

AU - Zimmermann, Horst

PY - 2012

Y1 - 2012

N2 - This work presents the design and performance of a 2.5Gbit/s transimpedance amplifier (TIA) for optical receivers implemented in a 40nm CMOS technology. The TIA is based on an inverting voltage amplifier with a shunt feedback resistor using noise cancelling technique to reduce the input noise. The TIA is followed by two stages of differential limiting amplifiers and the last stage is a 50 differential output driver to provide an interface to the measurement setup. The TIA shows a post layout simulated optical sensitivity of 25dBm for a BER= 10 12 and an optical power dynamic range of 25dB. The complete chip achieves a transimpedance gain of 79.5dB, 1.5GHz bandwidth and occupies a chip area of 0.16mm 2. The power consumption of the TIA is only 4.5mW and the complete chip dissipates 15mW for a 1.1V single supply voltage.

AB - This work presents the design and performance of a 2.5Gbit/s transimpedance amplifier (TIA) for optical receivers implemented in a 40nm CMOS technology. The TIA is based on an inverting voltage amplifier with a shunt feedback resistor using noise cancelling technique to reduce the input noise. The TIA is followed by two stages of differential limiting amplifiers and the last stage is a 50 differential output driver to provide an interface to the measurement setup. The TIA shows a post layout simulated optical sensitivity of 25dBm for a BER= 10 12 and an optical power dynamic range of 25dB. The complete chip achieves a transimpedance gain of 79.5dB, 1.5GHz bandwidth and occupies a chip area of 0.16mm 2. The power consumption of the TIA is only 4.5mW and the complete chip dissipates 15mW for a 1.1V single supply voltage.

UR - http://www.scopus.com/inward/record.url?scp=84866599645&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84866599645&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2012.6271599

DO - 10.1109/ISCAS.2012.6271599

M3 - Paper

AN - SCOPUS:84866599645

SP - 1740

EP - 1743

T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

Y2 - 20 May 2012 through 23 May 2012

ER -

2.5Gbit/s transimpedance amplifier using noise cancelling for optical receivers

Abstract

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this