Abstract
This work presents the design and performance of a 2.5Gbit/s transimpedance amplifier (TIA) for optical receivers implemented in a 40nm CMOS technology. The TIA is based on an inverting voltage amplifier with a shunt feedback resistor using noise cancelling technique to reduce the input noise. The TIA is followed by two stages of differential limiting amplifiers and the last stage is a 50 differential output driver to provide an interface to the measurement setup. The TIA shows a post layout simulated optical sensitivity of 25dBm for a BER= 10 12 and an optical power dynamic range of 25dB. The complete chip achieves a transimpedance gain of 79.5dB, 1.5GHz bandwidth and occupies a chip area of 0.16mm 2. The power consumption of the TIA is only 4.5mW and the complete chip dissipates 15mW for a 1.1V single supply voltage.
Original language | English |
---|---|
Pages | 1740-1743 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 2012 |
Externally published | Yes |
Event | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: May 20 2012 → May 23 2012 |
Conference
Conference | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 |
---|---|
Country/Territory | Korea, Republic of |
City | Seoul |
Period | 5/20/12 → 5/23/12 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering