2.5Gbit/s transimpedance amplifier using noise cancelling for optical receivers

Mohamed Atef; Horst Zimmermann

doi:10.1109/ISCAS.2012.6271599

2.5Gbit/s transimpedance amplifier using noise cancelling for optical receivers

Mohamed Atef, Horst Zimmermann

Research output: Contribution to conference › Paper › peer-review

26 Citations (Scopus)

Abstract

This work presents the design and performance of a 2.5Gbit/s transimpedance amplifier (TIA) for optical receivers implemented in a 40nm CMOS technology. The TIA is based on an inverting voltage amplifier with a shunt feedback resistor using noise cancelling technique to reduce the input noise. The TIA is followed by two stages of differential limiting amplifiers and the last stage is a 50 differential output driver to provide an interface to the measurement setup. The TIA shows a post layout simulated optical sensitivity of 25dBm for a BER= 10 ¹² and an optical power dynamic range of 25dB. The complete chip achieves a transimpedance gain of 79.5dB, 1.5GHz bandwidth and occupies a chip area of 0.16mm ². The power consumption of the TIA is only 4.5mW and the complete chip dissipates 15mW for a 1.1V single supply voltage.

Original language	English
Pages	1740-1743
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271599
Publication status	Published - 2012
Externally published	Yes
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: May 20 2012 → May 23 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	5/20/12 → 5/23/12

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2012.6271599

Cite this

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abstract = "This work presents the design and performance of a 2.5Gbit/s transimpedance amplifier (TIA) for optical receivers implemented in a 40nm CMOS technology. The TIA is based on an inverting voltage amplifier with a shunt feedback resistor using noise cancelling technique to reduce the input noise. The TIA is followed by two stages of differential limiting amplifiers and the last stage is a 50 differential output driver to provide an interface to the measurement setup. The TIA shows a post layout simulated optical sensitivity of 25dBm for a BER= 10 12 and an optical power dynamic range of 25dB. The complete chip achieves a transimpedance gain of 79.5dB, 1.5GHz bandwidth and occupies a chip area of 0.16mm 2. The power consumption of the TIA is only 4.5mW and the complete chip dissipates 15mW for a 1.1V single supply voltage.",

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year = "2012",

doi = "10.1109/ISCAS.2012.6271599",

language = "English",

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note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

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AU - Zimmermann, Horst

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AB - This work presents the design and performance of a 2.5Gbit/s transimpedance amplifier (TIA) for optical receivers implemented in a 40nm CMOS technology. The TIA is based on an inverting voltage amplifier with a shunt feedback resistor using noise cancelling technique to reduce the input noise. The TIA is followed by two stages of differential limiting amplifiers and the last stage is a 50 differential output driver to provide an interface to the measurement setup. The TIA shows a post layout simulated optical sensitivity of 25dBm for a BER= 10 12 and an optical power dynamic range of 25dB. The complete chip achieves a transimpedance gain of 79.5dB, 1.5GHz bandwidth and occupies a chip area of 0.16mm 2. The power consumption of the TIA is only 4.5mW and the complete chip dissipates 15mW for a 1.1V single supply voltage.

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2.5Gbit/s transimpedance amplifier using noise cancelling for optical receivers

Abstract

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