TY - GEN
T1 - 4 ps Resolution Time-to-Digital Converter Implementation Utilizing LUTs
AU - Hares, Khadiga
AU - Atef, Mohamed
AU - Sayed, Usama
AU - Ramzy, Safwat M.
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - In this work, a new approach for time-to-digital converter (TDC) was implemented and measured. The TDC is utilizing two ring oscillators, slow and fast oscillators. Ring oscillators that are used in the proposed scheme are implemented utilizing fast lookup tables. The editor floor planning was used to optimize the logic components placement and routing. The suggested TDC design was implemented and tested utilizing a Xilinx Virtex-5 field-programmable gate array. To ensure the effectiveness of the suggested design, the proposed system has been tested by both the simulation environment and the hardware measurement bench. The convergence between simulation results and measurement results reflects the accuracy and reliability of the proposed scheme. The TDC achieves a measured accuracy of 4 ps. The obtained results show the superiority of the proposed system compared to the related work.
AB - In this work, a new approach for time-to-digital converter (TDC) was implemented and measured. The TDC is utilizing two ring oscillators, slow and fast oscillators. Ring oscillators that are used in the proposed scheme are implemented utilizing fast lookup tables. The editor floor planning was used to optimize the logic components placement and routing. The suggested TDC design was implemented and tested utilizing a Xilinx Virtex-5 field-programmable gate array. To ensure the effectiveness of the suggested design, the proposed system has been tested by both the simulation environment and the hardware measurement bench. The convergence between simulation results and measurement results reflects the accuracy and reliability of the proposed scheme. The TDC achieves a measured accuracy of 4 ps. The obtained results show the superiority of the proposed system compared to the related work.
KW - FPGA
KW - TDC converters
KW - VHDL
UR - http://www.scopus.com/inward/record.url?scp=85126807003&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85126807003&partnerID=8YFLogxK
U2 - 10.1109/JAC-ECC54461.2021.9691418
DO - 10.1109/JAC-ECC54461.2021.9691418
M3 - Conference contribution
AN - SCOPUS:85126807003
T3 - Proceedings of the 2021 International Japan-Africa Conference on Electronics, Communications, and Computations, JAC-ECC 2021
SP - 53
EP - 56
BT - Proceedings of the 2021 International Japan-Africa Conference on Electronics, Communications, and Computations, JAC-ECC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 9th International Japan-Africa Conference on Electronics, Communications, and Computations, JAC-ECC 2021
Y2 - 13 December 2021 through 14 December 2021
ER -