This brief presents the design of an ultra-low power level-crossing analog-to-digital converter (LC-ADC) for IoT and biomedical applications. The proposed LC-ADC utilizes only one multi-level comparator instead of multiple comparators as in conventional LC-ADC, leading to simplified implementation and significant reduction in power. Implemented in 0.18-μ m CMOS process, the LC-ADC achieves 7.9 equivalent number of bits with a 49 dB signal-to-noise and distortion ratio at the input frequency up to 1 kHz. The measured minimum power is only 4.2 nW at the supply voltage of 0.55 V.
|Number of pages
|IEEE Transactions on Circuits and Systems II: Express Briefs
|Published - Oct 2018
- multi-level comparator
- ultra-low power
ASJC Scopus subject areas
- Electrical and Electronic Engineering