A 1.1 v 6.2 mW, wideband RF front-end for 0 dBm blocker tolerant receivers in 90 nm CMOS

Naveed Ahsan, Christer Svensson, Rashad Ramzan, Jerzy Dabrowski, Aziz Ouacha, Carl Samuelsson

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90 nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves a high linearity in a wide band (0.5-6 GHz. At very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8 dB up to 6 GHz. The measured single sideband noise figure at an LO frequency of 3 GHz and an if of 10 MHz is 6.25 dB. The front-end achieves a voltage conversion gain of 4.5 dB at 1 GHz with 3 dB bandwidth of more than 6 GHz. The measured input referred 1 dB compression point is +1.5 dBm while the IIP3 is +11.73 dBm and the IIP2 is +26.23 dBm respectively at an LO frequency of 2 GHz. The RF front-end consumes 6.2 mW from a 1.1 v supply with an active chip area of 0.0856 mm 2.

Original languageEnglish
Pages (from-to)79-90
Number of pages12
JournalAnalog Integrated Circuits and Signal Processing
Issue number1
Publication statusPublished - Jan 2012
Externally publishedYes


  • Blocker suppression
  • Common gate (CG)
  • Highly linear
  • Low IF receiver
  • Low power
  • Software defined radio
  • Wideband front-end

ASJC Scopus subject areas

  • Signal Processing
  • Hardware and Architecture
  • Surfaces, Coatings and Films


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