TY - JOUR
T1 - A 61-nW Level-Crossing ADC with Adaptive Sampling for Biomedical Applications
AU - Hou, Yuting
AU - Qu, Jiali
AU - Tian, Zhenzhen
AU - Atef, Mohamed
AU - Yousef, Khalil
AU - Lian, Yong
AU - Wang, Guoxing
N1 - Funding Information:
Manuscript received January 18, 2018; accepted May 3, 2018. Date of publication June 4, 2018; date of current version December 20, 2018. This work was supported in part by the Natural Science Foundation of China under Grant 61474074 and in part by the National Key Research and Development Program of China under Grant 2016YFC0105502. This brief was recommended by Associate Editor V. Saxena. (Corresponding author: Guoxing Wang.) Y. Hou, J. Qu, Z. Tian, Y. Lian, and G. Wang are with the Bio-Circuits and Systems Laboratory, Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai 200240, China (e-mail: guoxing@sjtu.edu.cn).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2019/1
Y1 - 2019/1
N2 - An ultra-low-power level-crossing analog-To-digital converter (LC-ADC) with on-chip adaptive sampling is presented. Different from conventional ADCs based on Nyquist sampling, LC-ADC utilizes sparsity of signals for low power data acquisition. To save power, the proposed adaptive sampling scheme is implemented with only one scaler and one high-precision comparator, which is in sharp contrast to conventional LC-ADCs that require an n-bit digital-To-Analog converter and two comparators. Implemented in 0.18-\mu {\mathrm{ m}} CMOS process, the proposed ADC consumes only 61 nW under 0.5V supply, and achieves 5.6 bits equivalent numbers of bits and 35 dB signal-To-noise and distortion ratio with an operating frequency up to 1 kHz.
AB - An ultra-low-power level-crossing analog-To-digital converter (LC-ADC) with on-chip adaptive sampling is presented. Different from conventional ADCs based on Nyquist sampling, LC-ADC utilizes sparsity of signals for low power data acquisition. To save power, the proposed adaptive sampling scheme is implemented with only one scaler and one high-precision comparator, which is in sharp contrast to conventional LC-ADCs that require an n-bit digital-To-Analog converter and two comparators. Implemented in 0.18-\mu {\mathrm{ m}} CMOS process, the proposed ADC consumes only 61 nW under 0.5V supply, and achieves 5.6 bits equivalent numbers of bits and 35 dB signal-To-noise and distortion ratio with an operating frequency up to 1 kHz.
KW - LC-ADC
KW - Ultra-low power
KW - on-chip adaptive sampling
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U2 - 10.1109/TCSII.2018.2841037
DO - 10.1109/TCSII.2018.2841037
M3 - Article
AN - SCOPUS:85059046733
SN - 1549-7747
VL - 66
SP - 56
EP - 60
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 1
M1 - 8371733
ER -