Abstract
An ultra-low-power level-crossing analog-To-digital converter (LC-ADC) with on-chip adaptive sampling is presented. Different from conventional ADCs based on Nyquist sampling, LC-ADC utilizes sparsity of signals for low power data acquisition. To save power, the proposed adaptive sampling scheme is implemented with only one scaler and one high-precision comparator, which is in sharp contrast to conventional LC-ADCs that require an n-bit digital-To-Analog converter and two comparators. Implemented in 0.18-\mu {\mathrm{ m}} CMOS process, the proposed ADC consumes only 61 nW under 0.5V supply, and achieves 5.6 bits equivalent numbers of bits and 35 dB signal-To-noise and distortion ratio with an operating frequency up to 1 kHz.
| Original language | English |
|---|---|
| Article number | 8371733 |
| Pages (from-to) | 56-60 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 66 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - Jan 2019 |
| Externally published | Yes |
Keywords
- LC-ADC
- Ultra-low power
- on-chip adaptive sampling
ASJC Scopus subject areas
- Electrical and Electronic Engineering