TY - GEN
T1 - A bayesian based EDA tool for accurate VLSI reliability evaluations
AU - Ibrahim, Walid
AU - Beg, Azam
AU - Amer, Hoda
PY - 2008/12/1
Y1 - 2008/12/1
N2 - As the sizes of (nano)device are aggressively scaled deep towards the nanometer regime, the design and manufacturing of future nano-circuits will become extremely complex and inevitably introduce more defects and their functioning will be adversely affected by transient faults. Therefore, accurately calculating the reliability of future designs will become a very important factor for nano-circuit designers as they investigate several design alternatives to optimize the trade-offs between the conflicting metrics of areapower-energy-delay versus reliability. This paper introduces a novel EDA tool for accurate calculation of future nano-circuits reliabilities. Our aim is to provide both educational and research institutions (as well as the semiconductor industry at a later stage) with an accurate and easy to use tool for comparing the reliability of different design alternatives, and for selecting the design that best fits a set of given (design) constraints.
AB - As the sizes of (nano)device are aggressively scaled deep towards the nanometer regime, the design and manufacturing of future nano-circuits will become extremely complex and inevitably introduce more defects and their functioning will be adversely affected by transient faults. Therefore, accurately calculating the reliability of future designs will become a very important factor for nano-circuit designers as they investigate several design alternatives to optimize the trade-offs between the conflicting metrics of areapower-energy-delay versus reliability. This paper introduces a novel EDA tool for accurate calculation of future nano-circuits reliabilities. Our aim is to provide both educational and research institutions (as well as the semiconductor industry at a later stage) with an accurate and easy to use tool for comparing the reliability of different design alternatives, and for selecting the design that best fits a set of given (design) constraints.
UR - http://www.scopus.com/inward/record.url?scp=67649472782&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=67649472782&partnerID=8YFLogxK
U2 - 10.1109/INNOVATIONS.2008.4781735
DO - 10.1109/INNOVATIONS.2008.4781735
M3 - Conference contribution
AN - SCOPUS:67649472782
SN - 9781424433971
T3 - 2008 International Conference on Innovations in Information Technology, IIT 2008
SP - 101
EP - 105
BT - 2008 International Conference on Innovations in Information Technology, IIT 2008
T2 - 2008 International Conference on Innovations in Information Technology, IIT 2008
Y2 - 16 December 2008 through 18 December 2008
ER -