A bayesian based EDA tool for accurate VLSI reliability evaluations

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

As the sizes of (nano)device are aggressively scaled deep towards the nanometer regime, the design and manufacturing of future nano-circuits will become extremely complex and inevitably introduce more defects and their functioning will be adversely affected by transient faults. Therefore, accurately calculating the reliability of future designs will become a very important factor for nano-circuit designers as they investigate several design alternatives to optimize the trade-offs between the conflicting metrics of areapower-energy-delay versus reliability. This paper introduces a novel EDA tool for accurate calculation of future nano-circuits reliabilities. Our aim is to provide both educational and research institutions (as well as the semiconductor industry at a later stage) with an accurate and easy to use tool for comparing the reliability of different design alternatives, and for selecting the design that best fits a set of given (design) constraints.

Original languageEnglish
Title of host publication2008 International Conference on Innovations in Information Technology, IIT 2008
Pages101-105
Number of pages5
DOIs
Publication statusPublished - Dec 1 2008
Event2008 International Conference on Innovations in Information Technology, IIT 2008 - Al Ain, United Arab Emirates
Duration: Dec 16 2008Dec 18 2008

Publication series

Name2008 International Conference on Innovations in Information Technology, IIT 2008

Other

Other2008 International Conference on Innovations in Information Technology, IIT 2008
Country/TerritoryUnited Arab Emirates
CityAl Ain
Period12/16/0812/18/08

ASJC Scopus subject areas

  • Computer Science Applications
  • Information Systems
  • Software

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