TY - GEN
T1 - A bayesian-based EDA tool for nano-circuits reliability calculations
AU - Ibrahim, Walid
AU - Beiu, Valeriu
PY - 2009
Y1 - 2009
N2 - As the sizes of (nano-)devices are aggressively scaled deep into the nanometer range, the design and manufacturing of future (nano-)circuits will become extremely complex and inevitably will introduce more defects while their functioning will be adversely affected by transient faults. Therefore, accurately calculating the reliability of future designs will become a very important aspect for (nano-)circuit designers as they investigate several design alternatives to optimize the trade-offs between the conflicting metrics of area-power-energy-delay versus reliability. This paper introduces a novel generic technique for the accurate calculation of the reliability of future nanocircuits. Our aim is to provide both educational and research institutions (as well as the semiconductor industry at a later stage) with an accurate and easy to use tool for closely comparing the reliability of different design alternatives, and for being able to easily select the design that best fits a set of given (design) constraints. Moreover, the reliability model generated by the tool should empower designers with the unique opportunity of understanding the influence individual gates play on the design's overall reliability, and identifying those (few) gates which impact the design's reliability most significantly.
AB - As the sizes of (nano-)devices are aggressively scaled deep into the nanometer range, the design and manufacturing of future (nano-)circuits will become extremely complex and inevitably will introduce more defects while their functioning will be adversely affected by transient faults. Therefore, accurately calculating the reliability of future designs will become a very important aspect for (nano-)circuit designers as they investigate several design alternatives to optimize the trade-offs between the conflicting metrics of area-power-energy-delay versus reliability. This paper introduces a novel generic technique for the accurate calculation of the reliability of future nanocircuits. Our aim is to provide both educational and research institutions (as well as the semiconductor industry at a later stage) with an accurate and easy to use tool for closely comparing the reliability of different design alternatives, and for being able to easily select the design that best fits a set of given (design) constraints. Moreover, the reliability model generated by the tool should empower designers with the unique opportunity of understanding the influence individual gates play on the design's overall reliability, and identifying those (few) gates which impact the design's reliability most significantly.
KW - Bayesian networks
KW - Eda tools
KW - Nano-circuits
KW - Reliability
UR - http://www.scopus.com/inward/record.url?scp=84885892311&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84885892311&partnerID=8YFLogxK
U2 - 10.1007/978-3-642-04850-0_36
DO - 10.1007/978-3-642-04850-0_36
M3 - Conference contribution
AN - SCOPUS:84885892311
SN - 3642048498
SN - 9783642048494
T3 - Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering
SP - 276
EP - 284
BT - Nano-Net - 4th International ICST Conference, Nano-Net 2009, Proceedings
T2 - 4th International ICST Conference on Nano-Net, Nano-Net 2009
Y2 - 18 October 2009 through 20 October 2009
ER -