A novel EDA tool for VLSI test vectors management

    Research output: Contribution to journalArticlepeer-review


    In today's semiconductor industry, where time-to-profit is a critical factor to remain competitive, missing the tight market window might have serious implications including the risk of product cancellation. This places severe pressure on every aspect related to the design and the verification of semiconductor chips to get the design ready for manufacturing in the shortest time possible. To avoid the need for costly corrective steps and silicon re-spins during post-silicon verification, thorough pre-silicon verification is essential to catch any design fault and estimate the design overall reliability before the design is manufactured. This paper presents a novel EDA tool that helps the verification team improve the verification process in several ways. It can be used to generate useful statistics regarding the complexity and the coverage of the created test vectors. Experimental results prove that the verification team can successfully use the proposed tool to set their target coverage and intelligently select the set of test vectors that achieves that target using the minimum number of computing cycles.

    Original languageEnglish
    Pages (from-to)421-434
    Number of pages14
    JournalJournal of Electronic Testing: Theory and Applications (JETTA)
    Issue number5
    Publication statusPublished - Oct 2007


    • EDA tools
    • Genetic algorithms
    • Test vectors selection
    • VLSI
    • Verification

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering


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