A reduced-dimension processor model: Incorporating microarchitectural parameters and software's dynamic characteristics

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    Architectural simulators used for microprocessor design study and optimization can require large amount of computational time and/or resources. In such cases, models can be a fast alternative to lengthy simulations, and can help reach a designer near-optimal system configuration. However, the non-linear characteristics of a processor system make the modeling task quite challenging. The models not only need to incorporate the micro-architectural parameters but also the dynamic behavior of programs. This paper presents a hybrid (hardware/software), non-linear model for processors. The model provides accurate predictions of processor throughput for a wide range of design space. We used different groups of code basic blocks to investigate their relationships to the execution efficiency of a superscalar processor. For this purpose, we utilized the frequencies of the blocks to represent runtime nature of ten benchmark programs. We were able to reduce the number of hardware and software parameters by employing correlation coefficients and principal component analysis.

    Original languageEnglish
    Title of host publicationAdvances in Machine Learning and Data Analysis
    Pages43-56
    Number of pages14
    DOIs
    Publication statusPublished - 2010
    EventInternational Conference on Advances in Machine Learning and Data Analysis - Berkeley, CA, United States
    Duration: Oct 22 2008Oct 24 2008

    Publication series

    NameLecture Notes in Electrical Engineering
    Volume48 LNEE
    ISSN (Print)1876-1100
    ISSN (Electronic)1876-1119

    Other

    OtherInternational Conference on Advances in Machine Learning and Data Analysis
    Country/TerritoryUnited States
    CityBerkeley, CA
    Period10/22/0810/24/08

    Keywords

    • Code basic blocks
    • Instructions per cycle (IPC)
    • Micro-architecture simulation
    • Processor model
    • Processor throughput prediction
    • Software dynamic behavior

    ASJC Scopus subject areas

    • Industrial and Manufacturing Engineering

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