TY - GEN
T1 - A reduced-dimension processor model
T2 - International Conference on Advances in Machine Learning and Data Analysis
AU - Beg, Azam
PY - 2010
Y1 - 2010
N2 - Architectural simulators used for microprocessor design study and optimization can require large amount of computational time and/or resources. In such cases, models can be a fast alternative to lengthy simulations, and can help reach a designer near-optimal system configuration. However, the non-linear characteristics of a processor system make the modeling task quite challenging. The models not only need to incorporate the micro-architectural parameters but also the dynamic behavior of programs. This paper presents a hybrid (hardware/software), non-linear model for processors. The model provides accurate predictions of processor throughput for a wide range of design space. We used different groups of code basic blocks to investigate their relationships to the execution efficiency of a superscalar processor. For this purpose, we utilized the frequencies of the blocks to represent runtime nature of ten benchmark programs. We were able to reduce the number of hardware and software parameters by employing correlation coefficients and principal component analysis.
AB - Architectural simulators used for microprocessor design study and optimization can require large amount of computational time and/or resources. In such cases, models can be a fast alternative to lengthy simulations, and can help reach a designer near-optimal system configuration. However, the non-linear characteristics of a processor system make the modeling task quite challenging. The models not only need to incorporate the micro-architectural parameters but also the dynamic behavior of programs. This paper presents a hybrid (hardware/software), non-linear model for processors. The model provides accurate predictions of processor throughput for a wide range of design space. We used different groups of code basic blocks to investigate their relationships to the execution efficiency of a superscalar processor. For this purpose, we utilized the frequencies of the blocks to represent runtime nature of ten benchmark programs. We were able to reduce the number of hardware and software parameters by employing correlation coefficients and principal component analysis.
KW - Code basic blocks
KW - Instructions per cycle (IPC)
KW - Micro-architecture simulation
KW - Processor model
KW - Processor throughput prediction
KW - Software dynamic behavior
UR - http://www.scopus.com/inward/record.url?scp=78651526412&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78651526412&partnerID=8YFLogxK
U2 - 10.1007/978-90-481-3177-8_4
DO - 10.1007/978-90-481-3177-8_4
M3 - Conference contribution
AN - SCOPUS:78651526412
SN - 9789048131761
T3 - Lecture Notes in Electrical Engineering
SP - 43
EP - 56
BT - Advances in Machine Learning and Data Analysis
Y2 - 22 October 2008 through 24 October 2008
ER -