A two-phase genetic algorithm for VLSI test vector selection

Design validation is one of the most complicated and costly tasks in today's system-on-chip development process. Conditions to be validated are identified by the architects, the designers, and the validation team. Testing for these conditions is a must for the design to tape out especially for high priority conditions. A significant bottleneck in such systems is that not enough time is normally given to the final coverage phase which makes computing cycles very precious. Thus, intelligent selection of test vectors that achieve the target coverage using the minimum number of computing cycles is crucial for on time tape out. This paper presents a two-phase genetic algorithm for test vector selection and condition coverage. The proposed algorithm significantly outperforms other proposed heuristic algorithms in different scenarios, while taking into considerations the conditions priorities and computing cycles required by each test vector.