TY - GEN
T1 - Accurate and effective algorithm for estimating the reliability of digital combinational circuits
AU - Ibrahim, Walid
PY - 2013
Y1 - 2013
N2 - Currently, with device geometries shrinking below 28nm, the available reliability margins of CMOS designs are drastically being reduced. This massive scaling deep into the nanometer range, will make the manufacture of future nano-circuits extremely complex and will introduce more defects, and more transient faults are expected to appear during operation. Hence, accurately calculating the reliability margins of future nano-circuits will become very critical for optimizing the trade-offs between the conflicting metrics of area-power-delay versus reliability. However, accurately calculating the reliability margins of large and highly connected circuits is a complex and very time consuming process. This paper presents an efficient and accurate solution for estimating the reliability of digital combinational circuits. The simulation results show that the solution is accurate enough and scales well with the circuit size and the length of the input vector.
AB - Currently, with device geometries shrinking below 28nm, the available reliability margins of CMOS designs are drastically being reduced. This massive scaling deep into the nanometer range, will make the manufacture of future nano-circuits extremely complex and will introduce more defects, and more transient faults are expected to appear during operation. Hence, accurately calculating the reliability margins of future nano-circuits will become very critical for optimizing the trade-offs between the conflicting metrics of area-power-delay versus reliability. However, accurately calculating the reliability margins of large and highly connected circuits is a complex and very time consuming process. This paper presents an efficient and accurate solution for estimating the reliability of digital combinational circuits. The simulation results show that the solution is accurate enough and scales well with the circuit size and the length of the input vector.
KW - Bayesian network.
KW - CMOS circuits
KW - Heuristic algorithms
KW - Optimization
KW - Reliability
UR - http://www.scopus.com/inward/record.url?scp=84876863848&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84876863848&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84876863848
SN - 9781627480307
T3 - Simulation Series
SP - 65
EP - 72
BT - Proceedings of the 2013 Spring Simulation Multiconference, SpringSim 2013 - 46th Annual Simulation Symposium, ANSS 2013
T2 - 46th Annual Simulation Symposium, ANSS 2013, Part of the 2013 Spring Simulation Multiconference, SpringSim 2013
Y2 - 7 April 2013 through 10 April 2013
ER -