Accurate Calculation of Unreliability of CMOS Logic Cells and Circuits

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1 Citation (Scopus)


Modern decananometer-sized MOS transistors tend to exhibit high rates of failure, underscoring the need for accurately estimating the unreliabilities of circuits built from such transistors. This paper presents a methodology for unreliability calculation that extends from individual transistors to complete logic circuits. As a logic cell's or logic circuit's unreliability is highly dependent on its transistors' drain-source and gate-source voltages, SPICE simulations are used to determine the voltages for the individual transistors. The voltage measurements are then utilized by the mathematical equations to predict the unreliabilities with high accuracy. A scalable framework based on the proposed methodology has been successfully implemented. The framework has been validated using ISCAS85 benchmark circuits.

Original languageEnglish
Article number2050202
JournalJournal of Circuits, Systems and Computers
Issue number13
Publication statusPublished - Oct 1 2020


  • CMOS integrated circuits
  • Circuit simulation
  • design optimization
  • fault tolerance
  • logic circuits
  • mathematical models
  • probability of failure
  • reliability
  • semiconductor device reliability

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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