Adder and Multiplier Circuits Employing Logic Gates Having Discrete, Weighted Inputs and Methods of Performing Combinatorial Operations Therewith

Valeriu Beiu

Adder and Multiplier Circuits Employing Logic Gates Having Discrete, Weighted Inputs and Methods of Performing Combinatorial Operations Therewith

Valeriu Beiu (Inventor)

Research output: Patent

Original language	English
Patent number	US 6,205,458
Publication status	Published - Mar 20 2001

Cite this

@misc{c71ef2bde2de460991ade3114a5125ba,

title = "Adder and Multiplier Circuits Employing Logic Gates Having Discrete, Weighted Inputs and Methods of Performing Combinatorial Operations Therewith",

author = "Valeriu Beiu",

note = "issueddate: 2001-3-20; US 6,205,458",

year = "2001",

month = mar,

day = "20",

language = "English",

type = "Patent",

}