Adder and Multiplier Circuits Employing Logic Gates Having Discrete, Weighted Inputs and Methods of Performing Combinatorial Operations Therewith

Valeriu Beiu

Adder and Multiplier Circuits Employing Logic Gates Having Discrete, Weighted Inputs and Methods of Performing Combinatorial Operations Therewith

Valeriu Beiu (Inventor)

Research output: Patent

Original language	English
Patent number	TW 481774
Publication status	Published - Apr 1 2002

Cite this

@misc{975c3fa605e04827a946ee1241a52ee8,

title = "Adder and Multiplier Circuits Employing Logic Gates Having Discrete, Weighted Inputs and Methods of Performing Combinatorial Operations Therewith",

author = "Valeriu Beiu",

note = "issueddate: 2002-4-1; TW 481774",

year = "2002",

month = apr,

day = "1",

language = "English",

type = "Patent",

}