| Original language | English |
|---|---|
| Patent number | US 6,502,120 |
| Publication status | Published - Dec 31 2002 |
Adder Circuits Employing Logic Gates Having Discrete Weighted Inputs and a Method of Operation Therewith
Valeriu Beiu (Inventor)
Research output: Patent
Valeriu Beiu (Inventor)
Research output: Patent
| Original language | English |
|---|---|
| Patent number | US 6,502,120 |
| Publication status | Published - Dec 31 2002 |