Addition Using Constrained Threshold Gates

Valeriu Beiu; Jan A. Peperstraete; Joos Vandewalle; Rudy Lauwereins

Addition Using Constrained Threshold Gates

Valeriu Beiu, Jan A. Peperstraete, Joos Vandewalle, Rudy Lauwereins

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper we show,that efficient VLSI implementations,of ADDITION are possible using constrained threshold gates (i.e. having limited fan-in and,range of weights). We introduce a class of Boolean functions F▲ and,while proving that ∀fΔ ∈ F▲ is linearly separable, we discover that each fΔ function can be built starting from the previous one (fΔ-2) by copying,its synaptic weights. As the G-functions computing,the carry bits are a subclass of F▲, we are able to build a set of “neural networks” for ADDITION with the fan-in (Δ) as a parameter, having depth = O (,lgn∕lglg n). Further directions for research are pointed out in the conclusions.

Original language	English
Title of host publication	International Conference on Technical Informatics
Publication status	Published - Nov 16 1994
Event	ConTI'95 - Timisoara, Romania Duration: Nov 16 1994 → …

Conference

Conference	ConTI'95
Period	11/16/94 → …

Cite this

@inproceedings{722ba954c7574f459c08560ac54a1839,

title = "Addition Using Constrained Threshold Gates",

abstract = "In this paper we show,that efficient VLSI implementations,of ADDITION are possible using constrained threshold gates (i.e. having limited fan-in and,range of weights). We introduce a class of Boolean functions F▲ and,while proving that ∀fΔ ∈ F▲ is linearly separable, we discover that each fΔ function can be built starting from the previous one (fΔ-2) by copying,its synaptic weights. As the G-functions computing,the carry bits are a subclass of F▲, we are able to build a set of “neural networks” for ADDITION with the fan-in (Δ) as a parameter, having depth = O (,lgn∕lglg n). Further directions for research are pointed out in the conclusions.",

author = "Valeriu Beiu and Peperstraete, {Jan A.} and Joos Vandewalle and Rudy Lauwereins",

year = "1994",

month = nov,

day = "16",

language = "English",

booktitle = "International Conference on Technical Informatics",

note = "ConTI'95 ; Conference date: 16-11-1994",

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TY - GEN

T1 - Addition Using Constrained Threshold Gates

AU - Beiu, Valeriu

AU - Peperstraete, Jan A.

AU - Vandewalle, Joos

AU - Lauwereins, Rudy

PY - 1994/11/16

Y1 - 1994/11/16

N2 - In this paper we show,that efficient VLSI implementations,of ADDITION are possible using constrained threshold gates (i.e. having limited fan-in and,range of weights). We introduce a class of Boolean functions F▲ and,while proving that ∀fΔ ∈ F▲ is linearly separable, we discover that each fΔ function can be built starting from the previous one (fΔ-2) by copying,its synaptic weights. As the G-functions computing,the carry bits are a subclass of F▲, we are able to build a set of “neural networks” for ADDITION with the fan-in (Δ) as a parameter, having depth = O (,lgn∕lglg n). Further directions for research are pointed out in the conclusions.

AB - In this paper we show,that efficient VLSI implementations,of ADDITION are possible using constrained threshold gates (i.e. having limited fan-in and,range of weights). We introduce a class of Boolean functions F▲ and,while proving that ∀fΔ ∈ F▲ is linearly separable, we discover that each fΔ function can be built starting from the previous one (fΔ-2) by copying,its synaptic weights. As the G-functions computing,the carry bits are a subclass of F▲, we are able to build a set of “neural networks” for ADDITION with the fan-in (Δ) as a parameter, having depth = O (,lgn∕lglg n). Further directions for research are pointed out in the conclusions.

M3 - Conference contribution

BT - International Conference on Technical Informatics

T2 - ConTI'95

Y2 - 16 November 1994

ER -

Addition Using Constrained Threshold Gates

Abstract

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