An adaptive genetic algorithm for VLSI test vector selection

The design complexity of today's System-on-Chip solutions has made the validation phase one of the most critical phases of the whole development process. Conditions to be validated are identified by the architects, the designers, and the validation team. Testing for these conditions is a must for the design to tape out especially these conditions with high priorities. A significant bottleneck in the validation process of such systems is that not enough time is normally given to the final coverage phase. Thus, intelligent selection of test vectors that achieves the target coverage using the minimum computing cycles is crucial for on time tape out. This paper presents two novel adaptive genetic algorithms for test vector selection and condition coverage. The proposed algorithms find a good set of test vectors that fulfills the target coverage under different scenarios, while taking into considerations operations priority, and computing cycles required by each test vector.