An adaptive heuristic algorithm for VLSI test vectors selection

Walid Ibrahim, Hesham El-Sayed, Amr El-Chouemie, Hoda Amer

Research output: Contribution to journalArticlepeer-review


The increasing complexity of today's system-on-a-chip designs is putting more pressure on the already stressed design verification process. The verification plan must cover several individual cores as well as the overall chip design. Conditions to be verified are identified by the system's architects, the designers, and the verification team. Testing for these conditions is a must for the design to tape out, especially for high priority conditions. A significant bottleneck in the verification process of such designs is that not enough time is usually given to the final coverage phase, which makes computing cycles very precious. Thus, intelligent selection of test vectors that achieve the best coverage using the minimum number of computing cycles is crucial for on time tape out. This paper presents a novel heuristic algorithm for test vectors selection. The algorithm attempts to achieve the best coverage level while minimizing the required number of computing cycles.

Original languageEnglish
Pages (from-to)630-639
Number of pages10
JournalEuropean Journal of Operational Research
Issue number3
Publication statusPublished - Dec 16 2009


  • Heuristic algorithms
  • Integer programming
  • SCP
  • VLSI
  • Verification

ASJC Scopus subject areas

  • General Computer Science
  • Modelling and Simulation
  • Management Science and Operations Research
  • Information Systems and Management


Dive into the research topics of 'An adaptive heuristic algorithm for VLSI test vectors selection'. Together they form a unique fingerprint.

Cite this