Scaling the CMOS transistors have been used consistently over the last five decades by the semiconductor industry to develop smaller, faster, and cheaper electronic devices. However, the massive scaling of CMOS devices deep into the deca-nanometer range has significantly reduced their reliability margins, and increased their vulnerability to both transient and permanent faults. Hence, incorporating some form of redundancy in the design of logic circuits is becoming a necessity for ensuring reliable operation. Nevertheless, incorporating redundancy for improving reliability is always a trade-off for increased area and more complex connectivity, which normally lead to higher delay and power consumption. Therefore, there is a need for electronic design automation tools for optimizing the design these conflicting goals. This paper introduces a highly efficient and accurate algorithm to calculate the circuit’s reliability based on the vulnerability of the circuit's output signals to the failure of the individual gates. Simulation results show that, due to the error masking ability of the logic gates, some gates could have much higher impact on the circuit’s reliability than the others. Improving the reliability of these gates would improve the circuit’s reliability effectively, while having minimum impact on the design area, delay, and power consumption.