An improved topology of SEPIC converter with reduced output voltage ripple

Mustafa A. Al-Saffar; Esam H. Ismail; Ahmad J. Sabzali; Abbas A. Fardoun

doi:10.1109/TPEL.2008.2001916

An improved topology of SEPIC converter with reduced output voltage ripple

Mustafa A. Al-Saffar, Esam H. Ismail, Ahmad J. Sabzali, Abbas A. Fardoun

Department of Electrical and Communication Engineering

Research output: Contribution to journal › Article › peer-review

66 Citations (Scopus)

Abstract

An improved version of a single-ended primary inductor converter (SEPIC) is presented. The converter consists of a conventional SEPIC converter plus an additional high-frequency transformer and diode to maintain a freewheeling mode of the dc inductor currents during the switch on state. The voltage conversion ratio characteristics and semiconductor device voltage and current stresses are characterized. The main advantages of this converter are the continuous output current, smaller output voltage ripple, and lower semiconductors current stress compared with the conventional SEPIC converter. The design and simulation of the concept is verified by an experiment with a 48-V input and 12-V/3.75-A output converter.

Original language	English
Pages (from-to)	2377-2386
Number of pages	10
Journal	IEEE Transactions on Power Electronics
Volume	23
Issue number	5
DOIs	https://doi.org/10.1109/TPEL.2008.2001916
Publication status	Published - 2008

Keywords

Active clamp
Continuous conduction mode (CCM)
Dc-Dc power conversion
Ripple reduction
Single-ended primary inductor converter (SEPIC)

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TPEL.2008.2001916

Cite this

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title = "An improved topology of SEPIC converter with reduced output voltage ripple",

abstract = "An improved version of a single-ended primary inductor converter (SEPIC) is presented. The converter consists of a conventional SEPIC converter plus an additional high-frequency transformer and diode to maintain a freewheeling mode of the dc inductor currents during the switch on state. The voltage conversion ratio characteristics and semiconductor device voltage and current stresses are characterized. The main advantages of this converter are the continuous output current, smaller output voltage ripple, and lower semiconductors current stress compared with the conventional SEPIC converter. The design and simulation of the concept is verified by an experiment with a 48-V input and 12-V/3.75-A output converter.",

keywords = "Active clamp, Continuous conduction mode (CCM), Dc-Dc power conversion, Ripple reduction, Single-ended primary inductor converter (SEPIC)",

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language = "English",

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T1 - An improved topology of SEPIC converter with reduced output voltage ripple

AU - Al-Saffar, Mustafa A.

AU - Ismail, Esam H.

AU - Sabzali, Ahmad J.

AU - Fardoun, Abbas A.

PY - 2008

Y1 - 2008

N2 - An improved version of a single-ended primary inductor converter (SEPIC) is presented. The converter consists of a conventional SEPIC converter plus an additional high-frequency transformer and diode to maintain a freewheeling mode of the dc inductor currents during the switch on state. The voltage conversion ratio characteristics and semiconductor device voltage and current stresses are characterized. The main advantages of this converter are the continuous output current, smaller output voltage ripple, and lower semiconductors current stress compared with the conventional SEPIC converter. The design and simulation of the concept is verified by an experiment with a 48-V input and 12-V/3.75-A output converter.

AB - An improved version of a single-ended primary inductor converter (SEPIC) is presented. The converter consists of a conventional SEPIC converter plus an additional high-frequency transformer and diode to maintain a freewheeling mode of the dc inductor currents during the switch on state. The voltage conversion ratio characteristics and semiconductor device voltage and current stresses are characterized. The main advantages of this converter are the continuous output current, smaller output voltage ripple, and lower semiconductors current stress compared with the conventional SEPIC converter. The design and simulation of the concept is verified by an experiment with a 48-V input and 12-V/3.75-A output converter.

KW - Active clamp

KW - Continuous conduction mode (CCM)

KW - Dc-Dc power conversion

KW - Ripple reduction

KW - Single-ended primary inductor converter (SEPIC)

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JO - IEEE Transactions on Power Electronics

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An improved topology of SEPIC converter with reduced output voltage ripple

Abstract

Keywords

ASJC Scopus subject areas

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