Area-Time Performances of Some Neural Computations

Valeriu Beiu, Jan A. Peperstraete, Joos Vandewalle, Rudy Lauwereins

    Research output: Chapter in Book/Report/Conference proceedingConference contribution


    The paper aims to show that VLSI efficient implementations of Boolean functions (BFs) using threshold gates (TGs) are possible. First we detail depth-size tradeoffs for COMPARISON when implemented by TGs of variable fan-in (D); a class of polynomially bounded TG circuits having O (lgn ⁄ lgD) depth and O (n ⁄ D) size for any 3 £ D £ clgn, improves on the previous known size O (n). We then proceed to show how fan-in influences the range of weights and of thresholds, and extend these results to Fn,m, the class of functions of n variables having m groups of ones. We conclude that the fan-in could be used by VLSI designers for tuning the area-time performances of neural chips.
    Original languageEnglish
    Title of host publicationInternational Symposium on Signal Processing, Robotics and Artificial Neural Networks
    Publication statusPublished - Apr 25 1994
    EventSPRANN'94 - Lille, France
    Duration: Apr 25 1994 → …


    Period4/25/94 → …


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