Atto Joule CMOS Gates Using Reversed Sizing and W/L Swapping

Azam Beg, Valeriu Beiu, Walid Ibrahim

    Research output: Chapter in Book/Report/Conference proceedingConference contribution


    Voltage reduction is a very widely used low-power technique (as reducing dynamic power quadratically, and leakage power linearly) which does sacrifice performance. An alternate technique, which is much less explored/investigated, is to rely on currents instead. The paper presents a thorough but still preliminary comparison of a recently introduced CMOS design technique which limits/reduces currents, with both the conventional/classical CMOS design, and also with a fresh sub-threshold CMOS design specifically aimed for ultra-low power (ULP). The preliminary results reported here suggest that the new design could achieve: (i) significantly lower power than classical CMOS (20-60×) without drastically degrading performances (5-20×); (ii) much better performances (100-200×) than the ULP scheme considered at power levels which are manageable (10-40x); while (iv) surpassing both of them on power-delay-product (PDP) and energy-delay-product (EDP). In particular, our inverters in 16nm are able to break the atto-Joule barrier at 300mV, and exhibit a delay of about 9ns.
    Original languageEnglish
    Title of host publicationIEEE 9th International New Circuits and Systems Conference
    Publication statusPublished - Jun 26 2011
    EventNEWCAS'11 - Bordeaux, France
    Duration: Jun 26 2011 → …


    Period6/26/11 → …


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