Automating the CMOS Gate Sizing for Reduced Power/Energy

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)

    Abstract

    This paper presents a new method for sizing the transistors in CMOS gates as an enabling technique for green technology. The technique utilizes an efficient feedback-based system to optimize the transistors sizes in the gates with the fanins of 2 or more. The optimized NAND2-4 gates provide nearly 65% savings in power dissipation and 58% reduction in energy consumption, as compared to their normal, uniformly sized counterparts. Power and energy savings for NOR2-4 gates are up to 8% and 38%, respectively.

    Original languageEnglish
    Title of host publicationProceedings - 12th International Conference on Frontiers of Information Technology, FIT 2014
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages193-196
    Number of pages4
    ISBN (Electronic)9781479975051
    DOIs
    Publication statusPublished - 2014
    Event12th International Conference on Frontiers of Information Technology, FIT 2014 - Islamabad, Pakistan
    Duration: Dec 17 2014Dec 19 2014

    Publication series

    NameProceedings - 12th International Conference on Frontiers of Information Technology, FIT 2014

    Other

    Other12th International Conference on Frontiers of Information Technology, FIT 2014
    Country/TerritoryPakistan
    CityIslamabad
    Period12/17/1412/19/14

    Keywords

    • CMOS
    • logic gates
    • low-energy circuit
    • low-power circuit
    • proportional-integral-derivative (PID) feedback control
    • static noise margin
    • transistor sizing

    ASJC Scopus subject areas

    • Information Systems

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