@inproceedings{fd3e65781dcc43fdb64fcec53f967ed6,
title = "Automating the CMOS Gate Sizing for Reduced Power/Energy",
abstract = "This paper presents a new method for sizing the transistors in CMOS gates as an enabling technique for green technology. The technique utilizes an efficient feedback-based system to optimize the transistors sizes in the gates with the fanins of 2 or more. The optimized NAND2-4 gates provide nearly 65% savings in power dissipation and 58% reduction in energy consumption, as compared to their normal, uniformly sized counterparts. Power and energy savings for NOR2-4 gates are up to 8% and 38%, respectively.",
keywords = "CMOS, logic gates, low-energy circuit, low-power circuit, proportional-integral-derivative (PID) feedback control, static noise margin, transistor sizing",
author = "Azam Beg",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 12th International Conference on Frontiers of Information Technology, FIT 2014 ; Conference date: 17-12-2014 Through 19-12-2014",
year = "2014",
doi = "10.1109/FIT.2014.44",
language = "English",
series = "Proceedings - 12th International Conference on Frontiers of Information Technology, FIT 2014",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "193--196",
booktitle = "Proceedings - 12th International Conference on Frontiers of Information Technology, FIT 2014",
}