Binary signed digit adder design with error detection capability

F. Kharbash, G. M. Chaudhry

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Binary Signed Digit Number (BSDN) representation has been used to form constant time adders and high-speed multipliers due to the capability of carry-free addition and regular VLSI layout. In order to use that numbering system BSDN digit needs to be encoded into binary bits. One of the possible encoding schemes is the 1-out-of-3 encoding which is a subset of the m-out-of-n codes widely used for error detection and correction. In this work, the design of BSDN full adder cell using the 1-out-of-3 encoding with and without error detection capability is presented. Synthesis results showed that the constant delay feature of the BSDN adder is preserved in both cases. It also showed that the overall performance (delay, area and power) of BSDN adder depends on the effectiveness of the BSDN full adder used to construct it and the desired level of error detection capability.

Original languageEnglish
Title of host publication2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007, Proceedings
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007 - Sharjah, United Arab Emirates
Duration: Feb 12 2007Feb 15 2007

Publication series

Name2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007, Proceedings

Other

Other2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007
Country/TerritoryUnited Arab Emirates
CitySharjah
Period2/12/072/15/07

ASJC Scopus subject areas

  • Signal Processing

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