Built-in loopback test for IC RF transceivers

Jerzy J. Dabrowski, Rashad M. Ramzan

Research output: Contribution to journalArticlepeer-review

24 Citations (Scopus)

Abstract

The essentials of the on-chip loopback test for integrated RF transceivers are presented. The available on-chip baseband processor serves as a tester while the RF front-end is under test enabled by on-chip test attenuator and in some cases by an offset mixer, too. Various system-level tests, like bit error rate, error vector magnitude, or spectral measurements are discussed. By using this technique in mass production, the RF test equipment can be largely avoided and the test cost reduced. Different variants of the loopback setup including the bypassing technique and RF detectors to boost the chip testability are considered. The existing limitations and tradeoffs are discussed in terms of test feasibility, controllability, and observability versus the chip performance. The fault-oriented approach supported by sensitization technique is put in contrast to the functional test. Also the impact of production tolerances is addressed in terms of a simple statistical model and the detectability thresholds. This paper is based on the present and previous work of the authors, largely revised and upgraded to provide a comprehensive description of the on-chip loopback test. Simulation examples of practical communication transceivers such as WLAN and EDGE under test are also included.

Original languageEnglish
Article number5325816
Pages (from-to)933-946
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume18
Issue number6
DOIs
Publication statusPublished - Jun 2010
Externally publishedYes

Keywords

  • Built-in self test (BiST)
  • Design for testability (DfT)
  • Loopback test
  • On-chip test
  • RF test
  • RF transceivers
  • Structural test

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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