Abstract
Single electron technology (SET) is one of the future technologies distinguished by its small and low-power devices. SET also provides simple and elegant solutions for threshold-logic gates (TLGs). This paper presents the design of an optimal TLG adder implemented in SET. This 16-bit Kogge-Stone style adder was fully designed and simulated using a Monte Carlo simulator. The simulation results give a quantitative estimate of both the delay and the power dissipation of the adder. The characteristics of our novel adder are compared with recent results estimating the energy-delay characteristics of advanced CMOS adders.
| Original language | English |
|---|---|
| Pages (from-to) | III681-III684 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 3 |
| Publication status | Published - 2004 |
| Externally published | Yes |
| Event | 2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada Duration: May 23 2004 → May 26 2004 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering