Comparing simulations and graphical representations of complexities of benchmark and large-variable circuits

P. W.C. Prasad, Azam Beg, Ashutosh Kumar Singh

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    Abstract: In this work, we analyzes the relationship between randomly generated BooIean function complexity and the number of nodes in benchmark circuits using the Binary Decision Diagrams (BDD). We generated BDDs for several ISCAS benchmark circuits and derived the area complexity measure in terms of number of nodes. We demonstrate that the benchmarks and randomly generated Boolean functions behave similarly in terms of area complexity. The experiments were extended to a large number of variables to verify the complexity behavior. It was confirmed that the rise of the complexity graph is only important to calculate the circuit com plexities.

    Original languageEnglish
    Title of host publicationICETC 2010 - 2010 2nd International Conference on Education Technology and Computer
    PagesV5134-V5138
    DOIs
    Publication statusPublished - 2010
    Event2010 2nd International Conference on Education Technology and Computer, ICETC 2010 - Shanghai, China
    Duration: Jun 22 2010Jun 24 2010

    Publication series

    NameICETC 2010 - 2010 2nd International Conference on Education Technology and Computer
    Volume5

    Other

    Other2010 2nd International Conference on Education Technology and Computer, ICETC 2010
    Country/TerritoryChina
    CityShanghai
    Period6/22/106/24/10

    Keywords

    • Area complexity
    • Benchmark circuits
    • Binary decision diagram

    ASJC Scopus subject areas

    • Computer Science (miscellaneous)
    • Education

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