Considerations for phase accumulator design for direct digital frequency synthesizers

David J. Betowski; Valeria Beiu

doi:10.1109/ICNNSP.2003.1279240

Considerations for phase accumulator design for direct digital frequency synthesizers

David J. Betowski, Valeria Beiu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

17 Citations (Scopus)

Abstract

This paper reviews the approach of using a direct digital frequency synthesizer (DDFS) to generate high-resolution, fast switching frequencies for modem communication systems. Because these systems are required to have high speed and/or low power requirements, optimizing the phase accumulator (PA) component is a crucial design step. A mathematical model for estimating the speed-power tradeoffs of pipelined PAs will be presented. Simulations based on this model show that pipelining the PA to the maximum allowable number of stages provides the smallest latency, but at power consumptions significantly higher than a non-pipelined PA. The model can be used to estimate the optimal number of pipeline stages for given speed-power constraints.

Original language	English
Title of host publication	Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Pages	176-179
Number of pages	4
DOIs	https://doi.org/10.1109/ICNNSP.2003.1279240
Publication status	Published - 2003
Externally published	Yes
Event	2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 - Nanjing, China Duration: Dec 14 2003 → Dec 17 2003

Publication series

Name	Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Volume	1

Other

Other	2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Country/Territory	China
City	Nanjing
Period	12/14/03 → 12/17/03

ASJC Scopus subject areas

Signal Processing
Computer Networks and Communications

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10.1109/ICNNSP.2003.1279240

Cite this

Betowski, D. J., & Beiu, V. (2003). Considerations for phase accumulator design for direct digital frequency synthesizers. In Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 (pp. 176-179). [1279240] (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03; Vol. 1). https://doi.org/10.1109/ICNNSP.2003.1279240

Considerations for phase accumulator design for direct digital frequency synthesizers. / Betowski, David J.; Beiu, Valeria.
Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03. 2003. p. 176-179 1279240 (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Betowski, DJ & Beiu, V 2003, Considerations for phase accumulator design for direct digital frequency synthesizers. in Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03., 1279240, Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03, vol. 1, pp. 176-179, 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03, Nanjing, China, 12/14/03. https://doi.org/10.1109/ICNNSP.2003.1279240

@inproceedings{05d737722a86459e9561ba340b8967da,

title = "Considerations for phase accumulator design for direct digital frequency synthesizers",

abstract = "This paper reviews the approach of using a direct digital frequency synthesizer (DDFS) to generate high-resolution, fast switching frequencies for modem communication systems. Because these systems are required to have high speed and/or low power requirements, optimizing the phase accumulator (PA) component is a crucial design step. A mathematical model for estimating the speed-power tradeoffs of pipelined PAs will be presented. Simulations based on this model show that pipelining the PA to the maximum allowable number of stages provides the smallest latency, but at power consumptions significantly higher than a non-pipelined PA. The model can be used to estimate the optimal number of pipeline stages for given speed-power constraints.",

author = "Betowski, {David J.} and Valeria Beiu",

year = "2003",

doi = "10.1109/ICNNSP.2003.1279240",

language = "English",

isbn = "0780377028",

series = "Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03",

pages = "176--179",

booktitle = "Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03",

note = "2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 ; Conference date: 14-12-2003 Through 17-12-2003",

}

TY - GEN

T1 - Considerations for phase accumulator design for direct digital frequency synthesizers

AU - Betowski, David J.

AU - Beiu, Valeria

PY - 2003

Y1 - 2003

N2 - This paper reviews the approach of using a direct digital frequency synthesizer (DDFS) to generate high-resolution, fast switching frequencies for modem communication systems. Because these systems are required to have high speed and/or low power requirements, optimizing the phase accumulator (PA) component is a crucial design step. A mathematical model for estimating the speed-power tradeoffs of pipelined PAs will be presented. Simulations based on this model show that pipelining the PA to the maximum allowable number of stages provides the smallest latency, but at power consumptions significantly higher than a non-pipelined PA. The model can be used to estimate the optimal number of pipeline stages for given speed-power constraints.

AB - This paper reviews the approach of using a direct digital frequency synthesizer (DDFS) to generate high-resolution, fast switching frequencies for modem communication systems. Because these systems are required to have high speed and/or low power requirements, optimizing the phase accumulator (PA) component is a crucial design step. A mathematical model for estimating the speed-power tradeoffs of pipelined PAs will be presented. Simulations based on this model show that pipelining the PA to the maximum allowable number of stages provides the smallest latency, but at power consumptions significantly higher than a non-pipelined PA. The model can be used to estimate the optimal number of pipeline stages for given speed-power constraints.

UR - http://www.scopus.com/inward/record.url?scp=12744262319&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=12744262319&partnerID=8YFLogxK

U2 - 10.1109/ICNNSP.2003.1279240

DO - 10.1109/ICNNSP.2003.1279240

M3 - Conference contribution

AN - SCOPUS:12744262319

SN - 0780377028

SN - 9780780377028

T3 - Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03

SP - 176

EP - 179

BT - Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03

T2 - 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03

Y2 - 14 December 2003 through 17 December 2003

ER -

Considerations for phase accumulator design for direct digital frequency synthesizers

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