Critical nodes count algorithm for accurate input vectors reliability ranking

Until recently digital circuit designers have relied on the highly reliable CMOS devices to implement small, fast, and power efficient circuits. However, as the CMOS devices are aggressively scaled deep into the nanometer scale, the fluctuations and variations at the device and gate levels have started to significantly affect the reliable operation of the nanocircuits. Since integrating redundancy schemes to mitigate the scaling effect and improve the circuit reliability will inevitably affect the design area, power, and delay parameters, accurate reliability enabled BOA tools should be introduced to help circuit designers to compare different reliability schemes and select the best one that optimize the trade-offs between reliability and the other conflicting design parameters. However, the enormous size and the complexity' of today's logic circuits makes accurate calculation of the circuit's reliability a very challenging and time consuming process. This paper studies the effect of the reconvergent fan- out nodes on the circuit's reliability and introduces an accurate reconvcrgcnt-bascd algorithm for input vector reliability ranking that significantly reduces the complexity of identifying the worst reliability input vector Simulation results show that proposed algorithm is efficient and more accurate than any other ranking algorithms currently proposed in the literature.