TY - GEN
T1 - Design layout optimization in the presence of proximity-dependent stress effects
AU - Sultan, Akif
AU - Ramzan, Rashad
AU - Wristers, Derick
PY - 2014
Y1 - 2014
N2 - In this paper, we present Minimized Layout Effect (MINLAYEF) guidelines for reducing the layout and process variations in critical analog circuits. We also present digital design guidelines to minimize the effect of process variations by eliminating stress sources. We also propose a layout for a reference device for a dual stress liner (DSL) device architecture to improve the accuracy of simulations. Si results from circuit layout designed with and without layout guidelines are also presented.
AB - In this paper, we present Minimized Layout Effect (MINLAYEF) guidelines for reducing the layout and process variations in critical analog circuits. We also present digital design guidelines to minimize the effect of process variations by eliminating stress sources. We also propose a layout for a reference device for a dual stress liner (DSL) device architecture to improve the accuracy of simulations. Si results from circuit layout designed with and without layout guidelines are also presented.
KW - DSL
KW - Layout guidelines
KW - Stress proximity effects
UR - http://www.scopus.com/inward/record.url?scp=84904174513&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84904174513&partnerID=8YFLogxK
U2 - 10.1109/ICICDT.2014.6838594
DO - 10.1109/ICICDT.2014.6838594
M3 - Conference contribution
AN - SCOPUS:84904174513
SN - 9781479921539
T3 - ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology
BT - ICICDT 2014 - IEEE International Conference on Integrated Circuit Design and Technology
PB - IEEE Computer Society
T2 - 2014 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2014
Y2 - 28 May 2014 through 30 May 2014
ER -