Designing array-based CMOS logic gates by using a feedback control system

    Research output: Contribution to journalConference articlepeer-review

    6 Citations (Scopus)


    This paper introduces an expedient method for designing nano-scaled CMOS logic gates based on minimumsized transistor arrays. NAND and NOR with fanins of 2 and 3 have been used to demonstrate the time-efficacy of the method based on a feedback control technique. The gates designed using the proposed scheme show improvement in terms of performance as well of power/energy consumption.

    Original languageEnglish
    Article number6974032
    Pages (from-to)935-939
    Number of pages5
    JournalConference Proceedings - IEEE International Conference on Systems, Man and Cybernetics
    Issue numberJanuary
    Publication statusPublished - 2014
    Event2014 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2014 - San Diego, United States
    Duration: Oct 5 2014Oct 8 2014


    • Energy consumption
    • Nano-scale CMOS logic gates
    • Performance
    • Power dissipation
    • Proportional-integral-derivative (PID) feedback control
    • Static noise margin
    • Transistor arrays

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Control and Systems Engineering
    • Human-Computer Interaction


    Dive into the research topics of 'Designing array-based CMOS logic gates by using a feedback control system'. Together they form a unique fingerprint.

    Cite this