Abstract
This paper introduces an expedient method for designing nano-scaled CMOS logic gates based on minimumsized transistor arrays. NAND and NOR with fanins of 2 and 3 have been used to demonstrate the time-efficacy of the method based on a feedback control technique. The gates designed using the proposed scheme show improvement in terms of performance as well of power/energy consumption.
Original language | English |
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Article number | 6974032 |
Pages (from-to) | 935-939 |
Number of pages | 5 |
Journal | Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics |
Volume | 2014-January |
Issue number | January |
DOIs | |
Publication status | Published - 2014 |
Event | 2014 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2014 - San Diego, United States Duration: Oct 5 2014 → Oct 8 2014 |
Keywords
- Energy consumption
- Nano-scale CMOS logic gates
- Performance
- Power dissipation
- Proportional-integral-derivative (PID) feedback control
- Static noise margin
- Transistor arrays
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Control and Systems Engineering
- Human-Computer Interaction