Designing array-based CMOS logic gates by using a feedback control system

Azam Beg

doi:10.1109/SMC.2014.6974032

Designing array-based CMOS logic gates by using a feedback control system

Azam Beg

Research output: Contribution to journal › Conference article › peer-review

6 Citations (Scopus)

Abstract

This paper introduces an expedient method for designing nano-scaled CMOS logic gates based on minimumsized transistor arrays. NAND and NOR with fanins of 2 and 3 have been used to demonstrate the time-efficacy of the method based on a feedback control technique. The gates designed using the proposed scheme show improvement in terms of performance as well of power/energy consumption.

Original language	English
Article number	6974032
Pages (from-to)	935-939
Number of pages	5
Journal	Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics
Volume	2014-January
Issue number	January
DOIs	https://doi.org/10.1109/SMC.2014.6974032
Publication status	Published - 2014
Event	2014 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2014 - San Diego, United States Duration: Oct 5 2014 → Oct 8 2014

Keywords

Energy consumption
Nano-scale CMOS logic gates
Performance
Power dissipation
Proportional-integral-derivative (PID) feedback control
Static noise margin
Transistor arrays

ASJC Scopus subject areas

Electrical and Electronic Engineering
Control and Systems Engineering
Human-Computer Interaction

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10.1109/SMC.2014.6974032

Cite this

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abstract = "This paper introduces an expedient method for designing nano-scaled CMOS logic gates based on minimumsized transistor arrays. NAND and NOR with fanins of 2 and 3 have been used to demonstrate the time-efficacy of the method based on a feedback control technique. The gates designed using the proposed scheme show improvement in terms of performance as well of power/energy consumption.",

keywords = "Energy consumption, Nano-scale CMOS logic gates, Performance, Power dissipation, Proportional-integral-derivative (PID) feedback control, Static noise margin, Transistor arrays",

author = "Azam Beg",

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AB - This paper introduces an expedient method for designing nano-scaled CMOS logic gates based on minimumsized transistor arrays. NAND and NOR with fanins of 2 and 3 have been used to demonstrate the time-efficacy of the method based on a feedback control technique. The gates designed using the proposed scheme show improvement in terms of performance as well of power/energy consumption.

KW - Energy consumption

KW - Nano-scale CMOS logic gates

KW - Performance

KW - Power dissipation

KW - Proportional-integral-derivative (PID) feedback control

KW - Static noise margin

KW - Transistor arrays

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JO - Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics

JF - Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics

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T2 - 2014 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2014

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ER -

Designing array-based CMOS logic gates by using a feedback control system

Abstract

Keywords

ASJC Scopus subject areas

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