The emerging of smart, battery operated, handheld mobile electronics (e.g., PDA, notebooks, mobile phones), and the widespread use of wireless sensor networks have raised the demand for ultra-low power electronics. The scaling of CMOS devices deep into the nano-regime brings promise for smaller, faster, and cheaper computing systems. However, it also leads to several challenges including power consumption and dynamic parameters fluctuations/variations, as well as intrinsic and extrinsic noises, with significant effects on the novel power-reliability tradeoff. This paper studies the effect of threshold voltage variations on the reliability of five full adder cells. It starts from the device-level by estimating the effects threshold voltage variations play on the reliability of scaled CMOS transistors. These estimations are then used to accurately calculate the reliability of the Sum and Carry-out signals of the five full adder cells under investigation. The simulation results show that the five full adders have reliabilities which are quite similar and mimic the reliability of the elementary devices, hence being strongly influenced by these.