Devices and input vectors are shaping von neumann multiplexing

Valeriu Beiu, Walid Ibrahim

    Research output: Contribution to journalArticlepeer-review

    17 Citations (Scopus)

    Abstract

    This paper starts by reviewing many of the gate-level reliability analyses of von Neumann multiplexing (vN-MUX). It goes on to detail very accurate device-level (CMOS technology specific) analyses of vN-MUX with respect to threshold voltage variations, taking into account both the gates topology as well as the input vectors. Such results are essential for a clear understanding of vN-MUX when considering the unreliable behavior of future nanodevices. These analyses should change the view from the top as revealing a different picture from the well-known gate-level theoretical and simulation results. The findings presented here are also able to explain certain apparently abnormal behaviors of vN-MUX reported based on Monte Carlo simulations, and should have implications for the appraisal and the design of future fault-tolerant nanoarchitectures.

    Original languageEnglish
    Article number5510160
    Pages (from-to)606-616
    Number of pages11
    JournalIEEE Transactions on Nanotechnology
    Volume10
    Issue number3
    DOIs
    Publication statusPublished - May 2011

    Keywords

    • CMOS
    • fault-tolerance
    • multiplexing
    • nanoarchitecture
    • reliability
    • threshold voltage
    • variations

    ASJC Scopus subject areas

    • Computer Science Applications
    • Electrical and Electronic Engineering

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