Enhanced Threshold Gate Fan-In Reduction Algorithms

Valeriu Beiu, Jan Peperstraete, Rudy Lauwereins

    Research output: Chapter in Book/Report/Conference proceedingConference contribution


    The paper describes and improves on a Boolean neural network (NN) fan-in reduction algorithm, with a view to possible VLSI implementation of NNs using threshold gates (TGs). Constructive proofs are given for: (i) at least halving the size; (ii) reducing the depth from O(N) to O(log 2N). Lastly a fresh algorithm which reduces the size to polynomial is suggested.
    Original languageEnglish
    Title of host publicationInternational Conference on Young Computer Scientists
    Publication statusPublished - Jul 15 1993
    EventICYCS'93 - Beijing, China
    Duration: Jul 15 1993 → …


    Period7/15/93 → …


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