Enhanced Threshold Gate Fan-In Reduction Algorithms

Valeriu Beiu; Jan Peperstraete; Rudy Lauwereins

Enhanced Threshold Gate Fan-In Reduction Algorithms

Valeriu Beiu, Jan Peperstraete, Rudy Lauwereins

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The paper describes and improves on a Boolean neural network (NN) fan-in reduction algorithm, with a view to possible VLSI implementation of NNs using threshold gates (TGs). Constructive proofs are given for: (i) at least halving the size; (ii) reducing the depth from O(N) to O(log 2N). Lastly a fresh algorithm which reduces the size to polynomial is suggested.

Original language	English
Title of host publication	International Conference on Young Computer Scientists
Publication status	Published - Jul 15 1993
Event	ICYCS'93 - Beijing, China Duration: Jul 15 1993 → …

Conference

Conference	ICYCS'93
Period	7/15/93 → …

Access to Document

http://dl.acm.org/citation.cfm?id=173025; http://wenku.baidu.com/view/9b7f27d850e2524de5187e61.html

Cite this

@inproceedings{382e64f86b87465794706856d7505641,

title = "Enhanced Threshold Gate Fan-In Reduction Algorithms",

abstract = "The paper describes and improves on a Boolean neural network (NN) fan-in reduction algorithm, with a view to possible VLSI implementation of NNs using threshold gates (TGs). Constructive proofs are given for: (i) at least halving the size; (ii) reducing the depth from O(N) to O(log 2N). Lastly a fresh algorithm which reduces the size to polynomial is suggested.",

author = "Valeriu Beiu and Jan Peperstraete and Rudy Lauwereins",

year = "1993",

month = jul,

day = "15",

language = "English",

booktitle = "International Conference on Young Computer Scientists",

note = "ICYCS'93 ; Conference date: 15-07-1993",

}

TY - GEN

T1 - Enhanced Threshold Gate Fan-In Reduction Algorithms

AU - Beiu, Valeriu

AU - Peperstraete, Jan

AU - Lauwereins, Rudy

PY - 1993/7/15

Y1 - 1993/7/15

N2 - The paper describes and improves on a Boolean neural network (NN) fan-in reduction algorithm, with a view to possible VLSI implementation of NNs using threshold gates (TGs). Constructive proofs are given for: (i) at least halving the size; (ii) reducing the depth from O(N) to O(log 2N). Lastly a fresh algorithm which reduces the size to polynomial is suggested.

AB - The paper describes and improves on a Boolean neural network (NN) fan-in reduction algorithm, with a view to possible VLSI implementation of NNs using threshold gates (TGs). Constructive proofs are given for: (i) at least halving the size; (ii) reducing the depth from O(N) to O(log 2N). Lastly a fresh algorithm which reduces the size to polynomial is suggested.

M3 - Conference contribution

BT - International Conference on Young Computer Scientists

T2 - ICYCS'93

Y2 - 15 July 1993

ER -

Enhanced Threshold Gate Fan-In Reduction Algorithms

Abstract

Conference

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Cite this