Enhancing the static noise margins by upsizing length for ultra-low voltage/power/energy gates

This paper analyzes in details a novel transistor sizing method for classical CMOS gates implemented in advanced technology nodes and operating correctly over the whole voltage range, including ultra-low voltages. The method proposed recently relies on upsizing the length (L) of all transistors uniformly, and balancing the voltage transfer curves (VTCs) for maximizing the static noise margins (SNMs). In this paper we use five classical CMOS gates (INV, NAND-2, NOR-2, XOR-2, MAJ-3) for evaluating and comparing performances. Monte Carlo simulations are used for the first time for these gates and sizing method. The Monte Carlo simulation results show that the sizing method is able to improve even more than what was known from previous simulations (which did not consider statistical variations). This also proves that sizing in very fine increments has the potential to go beyond the well-established delay-power tradeoff, as it can significantly increase SNM's while also reducing power, and in many cases reducing the power-delay-product (PDP) also. Simulation results show that the sizing method enables much more reliable (i.e., noise-robust and variation-tolerant) CMOS gates, which could operate correctly at very low supply voltages, hence potentially paving the way to ultra-low voltage/power/energy circuits.