FPGA Optimization of Advanced Encryption Standard Algorithm for Biometric Images

This is a master thesis in the field of information security. The problem area addressed is how to efficiency implement encryption and decryption of biometric image data in a FPGA. The objective for the project was to implement AES (Advanced Encryption Standard ) encryption in a Xilinx Kintex-7 FPGA with biometric image data as the application. The method used in this project is Design Science Research Methodology, in total three design and development iterations were performed to achieve the project objectives. The end result is a FPGA platform designed for information security research with biometric image as application. The FPGA developed in this project, is the first fully pipelined AES encryption/decryption system to run physically in a Kintex-7 device. The encryption core was made by Dr. Qiang Liu and his team while the fully pipelined decryption core was designed in this project. The AES encryption/ decryptions was further optimized to support image application by adding Cipher-block chaining to both the encryption and decryption. The performance achieved for the system was 40 GB/s throughput, 5.27 Mb/slice efficiency with a power performance of 286 GB/W. The FPGA platform developed in this project is not only limited to AES, other cryptography standards can be implemented on the platform as well.