TY - GEN
T1 - From transistor variations to NAND-2 multiplexing
AU - Beiu, Valeriu
AU - Ibrahim, Walid
PY - 2010
Y1 - 2010
N2 - This paper will start by reviewing gate-level reliability analyses of NAND-2 multiplexing. The key reason we are focusing on multiplexing is that currently this is the most efficient redundancy scheme able to deal with faults (i.e., transient errors). The paper will explore NAND-2 multiplexing at the smallest redundancy factors of 9 (i.e., 3x3) and 15 (i.e., 3x5). Accurate device-level simulations starting from the threshold voltage variations of bulk CMOS transistors (in 32nm, 22nm, and 16nm) will be detailed, and their results will be presented and discussed. Such device-level reliability results for multiplexing are presented here for the first time ever. These analyses are essential for a clear understanding of how effective NAND-2 multiplexing is, especially when considering the expected unreliable behavior of future nanoscale devices. They show that device-level reliability results are different from the well-known gate-level reliability results, and should have implications for the design of future nano-architectures.
AB - This paper will start by reviewing gate-level reliability analyses of NAND-2 multiplexing. The key reason we are focusing on multiplexing is that currently this is the most efficient redundancy scheme able to deal with faults (i.e., transient errors). The paper will explore NAND-2 multiplexing at the smallest redundancy factors of 9 (i.e., 3x3) and 15 (i.e., 3x5). Accurate device-level simulations starting from the threshold voltage variations of bulk CMOS transistors (in 32nm, 22nm, and 16nm) will be detailed, and their results will be presented and discussed. Such device-level reliability results for multiplexing are presented here for the first time ever. These analyses are essential for a clear understanding of how effective NAND-2 multiplexing is, especially when considering the expected unreliable behavior of future nanoscale devices. They show that device-level reliability results are different from the well-known gate-level reliability results, and should have implications for the design of future nano-architectures.
UR - http://www.scopus.com/inward/record.url?scp=79951845440&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79951845440&partnerID=8YFLogxK
U2 - 10.1109/NANO.2010.5697864
DO - 10.1109/NANO.2010.5697864
M3 - Conference contribution
AN - SCOPUS:79951845440
SN - 9781424470334
T3 - 2010 10th IEEE Conference on Nanotechnology, NANO 2010
SP - 1076
EP - 1081
BT - 2010 10th IEEE Conference on Nanotechnology, NANO 2010
T2 - 2010 10th IEEE Conference on Nanotechnology, NANO 2010
Y2 - 17 August 2010 through 20 August 2010
ER -