TY - GEN
T1 - Grand challenges of nanoelectronics and possible architectural solutions what do Shannon, von Neumann, Kolmogorov, and Feynman have to do with Moore
AU - Beiu, Valeriu
PY - 2007
Y1 - 2007
N2 - This presentation will discuss the many challenges faced by the design of future tera-scale integrated circuits that result from the use of nano-scale electronic devices. The relations among these challenges will be studied, and a relative ranking will be proposed. Afterwards, we shall delve into the most difficult challenges. Finally, possible solutions will also be suggested.
AB - This presentation will discuss the many challenges faced by the design of future tera-scale integrated circuits that result from the use of nano-scale electronic devices. The relations among these challenges will be studied, and a relative ranking will be proposed. Afterwards, we shall delve into the most difficult challenges. Finally, possible solutions will also be suggested.
UR - http://www.scopus.com/inward/record.url?scp=34548283007&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34548283007&partnerID=8YFLogxK
U2 - 10.1109/ISMVL.2007.27
DO - 10.1109/ISMVL.2007.27
M3 - Conference contribution
AN - SCOPUS:34548283007
SN - 0769528317
SN - 9780769528311
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
BT - 37th International Symposium on Multiple-Valued Logic, ISMVL 2007
T2 - 37th International Symposium on Multiple-Valued Logic, ISMVL 2007
Y2 - 13 May 2007 through 16 May 2007
ER -