GREDA: A fast and more accurate gate reliability EDA tool

Walid Ibrahim; Valeriu Beiu; Azam Beg

doi:10.1109/TCAD.2011.2176123

GREDA: A fast and more accurate gate reliability EDA tool

Walid Ibrahim, Valeriu Beiu, Azam Beg

Research output: Contribution to journal › Article › peer-review

20 Citations (Scopus)

Abstract

Generic as well as customized reliability electronic design automation (EDA) tools have been proposed in the literature and used to estimate the reliability of both present and future (nano)circuits. However, the accuracy of many of these EDA tools is questionable as they: 1) either assume that all gates have the same constant probability of failure (PF _GATE=const.), or 2) use very simple approaches to estimate the reliability of the elementary gates. In this paper, we introduce a gate reliability EDA tool (GREDA) that is able to estimate more accurately the reliability of CMOS gates by considering: 1) the gate's topology; 2) the variable probability of failure of the individual devices (PF _DEV) 3) the applied input vector; 4) the reliability of the input signals; and 5) the input voltage variations (which can be linked to the allowed noise margins). GREDA can be used to calculate PF _GATE due to different types of faults and/or defects, and to estimate the effects of enhancing PF _DEV on PF _GATE. Simulation results show that GREDA can improve on the accuracy of reliability calculations at the gate level.

Original language	English
Article number	6171048
Pages (from-to)	509-521
Number of pages	13
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	31
Issue number	4
DOIs	https://doi.org/10.1109/TCAD.2011.2176123
Publication status	Published - Apr 2012

Keywords

Bayesian network
CMOS logic
circuit reliability
design automation
nanotechnology
reliability modeling

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/TCAD.2011.2176123

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@article{32db0220ea8148c09716ac6709ccf66f,

title = "GREDA: A fast and more accurate gate reliability EDA tool",

abstract = "Generic as well as customized reliability electronic design automation (EDA) tools have been proposed in the literature and used to estimate the reliability of both present and future (nano)circuits. However, the accuracy of many of these EDA tools is questionable as they: 1) either assume that all gates have the same constant probability of failure (PF GATE=const.), or 2) use very simple approaches to estimate the reliability of the elementary gates. In this paper, we introduce a gate reliability EDA tool (GREDA) that is able to estimate more accurately the reliability of CMOS gates by considering: 1) the gate's topology; 2) the variable probability of failure of the individual devices (PF DEV) 3) the applied input vector; 4) the reliability of the input signals; and 5) the input voltage variations (which can be linked to the allowed noise margins). GREDA can be used to calculate PF GATE due to different types of faults and/or defects, and to estimate the effects of enhancing PF DEV on PF GATE. Simulation results show that GREDA can improve on the accuracy of reliability calculations at the gate level.",

keywords = "Bayesian network, CMOS logic, circuit reliability, design automation, nanotechnology, reliability modeling",

author = "Walid Ibrahim and Valeriu Beiu and Azam Beg",

note = "Funding Information: Manuscript received February 20, 2011; revised May 23, 2011 and July 18, 2011; accepted October 24, 2011. Date of current version March 21, 2012. The work of W. Ibrahim was supported by the UAEU, under Grant #31T006, entitled “Nano-CRC: Novel algorithms, models and EDA tools for accurate nanocircuits reliability calculations.” The work of V. Beiu was supported in part by the UAEU, under Grant 1108-00451/2010, by the British Council (U.K.-UAEU PMI2 Connect Grant RC GS 271), and by a gift from Intel. This paper was recommended by Associate Editor M. Poncino. Funding Information: This document is an output from the PMI2 Project funded by the U.K. Department for Innovations, Universities and Skills (DIUS) for the Benefit of the United Arab Emirates Higher Education Sector and the U.K. Higher Education Sector. The views expressed are not necessarily those of DIUS nor the British Council.",

year = "2012",

month = apr,

doi = "10.1109/TCAD.2011.2176123",

language = "English",

volume = "31",

pages = "509--521",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - GREDA

T2 - A fast and more accurate gate reliability EDA tool

AU - Ibrahim, Walid

AU - Beiu, Valeriu

AU - Beg, Azam

N1 - Funding Information: Manuscript received February 20, 2011; revised May 23, 2011 and July 18, 2011; accepted October 24, 2011. Date of current version March 21, 2012. The work of W. Ibrahim was supported by the UAEU, under Grant #31T006, entitled “Nano-CRC: Novel algorithms, models and EDA tools for accurate nanocircuits reliability calculations.” The work of V. Beiu was supported in part by the UAEU, under Grant 1108-00451/2010, by the British Council (U.K.-UAEU PMI2 Connect Grant RC GS 271), and by a gift from Intel. This paper was recommended by Associate Editor M. Poncino. Funding Information: This document is an output from the PMI2 Project funded by the U.K. Department for Innovations, Universities and Skills (DIUS) for the Benefit of the United Arab Emirates Higher Education Sector and the U.K. Higher Education Sector. The views expressed are not necessarily those of DIUS nor the British Council.

PY - 2012/4

Y1 - 2012/4

N2 - Generic as well as customized reliability electronic design automation (EDA) tools have been proposed in the literature and used to estimate the reliability of both present and future (nano)circuits. However, the accuracy of many of these EDA tools is questionable as they: 1) either assume that all gates have the same constant probability of failure (PF GATE=const.), or 2) use very simple approaches to estimate the reliability of the elementary gates. In this paper, we introduce a gate reliability EDA tool (GREDA) that is able to estimate more accurately the reliability of CMOS gates by considering: 1) the gate's topology; 2) the variable probability of failure of the individual devices (PF DEV) 3) the applied input vector; 4) the reliability of the input signals; and 5) the input voltage variations (which can be linked to the allowed noise margins). GREDA can be used to calculate PF GATE due to different types of faults and/or defects, and to estimate the effects of enhancing PF DEV on PF GATE. Simulation results show that GREDA can improve on the accuracy of reliability calculations at the gate level.

AB - Generic as well as customized reliability electronic design automation (EDA) tools have been proposed in the literature and used to estimate the reliability of both present and future (nano)circuits. However, the accuracy of many of these EDA tools is questionable as they: 1) either assume that all gates have the same constant probability of failure (PF GATE=const.), or 2) use very simple approaches to estimate the reliability of the elementary gates. In this paper, we introduce a gate reliability EDA tool (GREDA) that is able to estimate more accurately the reliability of CMOS gates by considering: 1) the gate's topology; 2) the variable probability of failure of the individual devices (PF DEV) 3) the applied input vector; 4) the reliability of the input signals; and 5) the input voltage variations (which can be linked to the allowed noise margins). GREDA can be used to calculate PF GATE due to different types of faults and/or defects, and to estimate the effects of enhancing PF DEV on PF GATE. Simulation results show that GREDA can improve on the accuracy of reliability calculations at the gate level.

KW - Bayesian network

KW - CMOS logic

KW - circuit reliability

KW - design automation

KW - nanotechnology

KW - reliability modeling

UR - http://www.scopus.com/inward/record.url?scp=84859037145&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84859037145&partnerID=8YFLogxK

U2 - 10.1109/TCAD.2011.2176123

DO - 10.1109/TCAD.2011.2176123

M3 - Article

AN - SCOPUS:84859037145

SN - 0278-0070

VL - 31

SP - 509

EP - 521

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 4

M1 - 6171048

ER -

GREDA: A fast and more accurate gate reliability EDA tool

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