TY - GEN
T1 - Hardware Trojans in asynchronous FIFO-buffers
T2 - 58th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2015
AU - Hasan, Syed Rafay
AU - Mossa, Siraj Fulum
AU - Perez, Ciro
AU - Awwad, Falah
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/9/28
Y1 - 2015/9/28
N2 - System on chip (SoC) contains multiple intellectual properties (IPs) that work in different clock domains. Several of those IPs may even have multiple clock domains within itself and provided to SoC designers as hard IPs. Different clock domain crossing (CDC) techniques are used to communicate among different clock domains. First In First Out (FIFO) buffers are part of several CDC circuits. This research explores the possible security vulnerabilities of such SoCs in the event of compromised security in FIFO buffers. We investigated few catastrophic possibilities of hardware Trojans in FIFO buffers and discussed its potential consequences. Testing the design using random bit generation showed that the triggering probabilities of such Trojans are less than 8/1000. Our synthesis results show that majority of these Trojans require minimal area and frequency overhead, in the range of.8% and 1%, respectively, if FIFO occupies 10% space of the IP.
AB - System on chip (SoC) contains multiple intellectual properties (IPs) that work in different clock domains. Several of those IPs may even have multiple clock domains within itself and provided to SoC designers as hard IPs. Different clock domain crossing (CDC) techniques are used to communicate among different clock domains. First In First Out (FIFO) buffers are part of several CDC circuits. This research explores the possible security vulnerabilities of such SoCs in the event of compromised security in FIFO buffers. We investigated few catastrophic possibilities of hardware Trojans in FIFO buffers and discussed its potential consequences. Testing the design using random bit generation showed that the triggering probabilities of such Trojans are less than 8/1000. Our synthesis results show that majority of these Trojans require minimal area and frequency overhead, in the range of.8% and 1%, respectively, if FIFO occupies 10% space of the IP.
KW - First In First Out (FIFO)
KW - Hardware Trojan
KW - clock domain crossing
UR - http://www.scopus.com/inward/record.url?scp=84962088917&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84962088917&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2015.7282151
DO - 10.1109/MWSCAS.2015.7282151
M3 - Conference contribution
AN - SCOPUS:84962088917
T3 - Midwest Symposium on Circuits and Systems
BT - IEEE 58th International Midwest Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 2 August 2015 through 5 August 2015
ER -