High performance AES design using pipelining structure over GF((2 ⁴) ²)

High data throughput AES hardware architecture is proposed by partitioning the ten rounds into sub-blocks of repeated AES modules. The blocks are separated by intermediate buffers providing a complete ten stages of AES pipeline structure. Furthermore, the AES is internally evenly divided to ten pipeline stages; with the addition feature that the shift rows block (ShiftRow) is structured to operate before the byte substitute (Byte Substitute) block. The use of this swapping operation has no effect on the AES encryption algorithm; however, it streamlines the process of four blocks of data in parallel rather than 16 blocks which is considered the key advantage for area saving. We evaluate the performance of our new implementation and current implementations in terms of throughput rate and hardware area for ALTERA MAX3000A family FPGA EMP3128ATC100-5. The simulation results show that the proposed AES has higher throughput rate of about 16% than the general AES pipeline structure with a saving hardware area of 36%.