High performance AES design using pipelining structure over GF((2 4) 2)

Saleh Abdel-hafeez, Ahmed Sawalmeh, Sameer Bataineh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

High data throughput AES hardware architecture is proposed by partitioning the ten rounds into sub-blocks of repeated AES modules. The blocks are separated by intermediate buffers providing a complete ten stages of AES pipeline structure. Furthermore, the AES is internally evenly divided to ten pipeline stages; with the addition feature that the shift rows block (ShiftRow) is structured to operate before the byte substitute (Byte Substitute) block. The use of this swapping operation has no effect on the AES encryption algorithm; however, it streamlines the process of four blocks of data in parallel rather than 16 blocks which is considered the key advantage for area saving. We evaluate the performance of our new implementation and current implementations in terms of throughput rate and hardware area for ALTERA MAX3000A family FPGA EMP3128ATC100-5. The simulation results show that the proposed AES has higher throughput rate of about 16% than the general AES pipeline structure with a saving hardware area of 36%.

Original languageEnglish
Title of host publicationICSPC 2007 Proceedings - 2007 IEEE International Conference on Signal Processing and Communications
Pages716-719
Number of pages4
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 IEEE International Conference on Signal Processing and Communications, ICSPC 2007 - Dubai, United Arab Emirates
Duration: Nov 14 2007Nov 27 2007

Publication series

NameICSPC 2007 Proceedings - 2007 IEEE International Conference on Signal Processing and Communications

Other

Other2007 IEEE International Conference on Signal Processing and Communications, ICSPC 2007
Country/TerritoryUnited Arab Emirates
CityDubai
Period11/14/0711/27/07

Keywords

  • AES pipeline
  • FPGA
  • GF((2 ) )
  • Rijndael
  • S-box

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Signal Processing
  • Communication

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