TY - GEN
T1 - High performance fast multiplier
AU - Chaudhary, G. M.
AU - Kharbash, F.
PY - 2008
Y1 - 2008
N2 - Binary multiplication is very crucial arithmetic operations in digital signal processing systems as well as general computer systems because the performance of the processor is significantly influenced by the speed of their multipliers. In this paper, we present a design-methodology for high-speed multiplications, where two integers of n-bit size each are multiplied to produce a 2n-bit product. This paper presents an efficient method for performing multiplications in one step from the least significant bit towards the most significant bit.
AB - Binary multiplication is very crucial arithmetic operations in digital signal processing systems as well as general computer systems because the performance of the processor is significantly influenced by the speed of their multipliers. In this paper, we present a design-methodology for high-speed multiplications, where two integers of n-bit size each are multiplied to produce a 2n-bit product. This paper presents an efficient method for performing multiplications in one step from the least significant bit towards the most significant bit.
KW - Carry-adders
KW - High performance fast multiplier
KW - Least signifying bet
KW - Most significant bit
KW - Overflow
KW - Partial products
KW - Product term
KW - Product values
UR - http://www.scopus.com/inward/record.url?scp=51849084801&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=51849084801&partnerID=8YFLogxK
U2 - 10.1109/TPSD.2008.4562751
DO - 10.1109/TPSD.2008.4562751
M3 - Conference contribution
AN - SCOPUS:51849084801
SN - 9781424420773
T3 - 2008 IEEE Region 5 Conference
BT - 2008 IEEE Region 5 Conference
T2 - 2008 IEEE Region 5 Conference
Y2 - 17 April 2008 through 20 April 2008
ER -