High-speed photodiodes in 40 nm standard CMOS technology

This work investigates two silicon (Si) photodiodes (PDs) fabricated in 40 nm standard CMOS technology. The basic structure of the proposed Si PD is formed by N+/P-substrate and N-well/P-substrate diodes. The N+/P-substrate PD demonstrates a responsivity of 0.09 A/W and an electrical bandwidth of 3 GHz for 8 V reverse bias at 520 nm. The N-well/P-substrate PD demonstrates a responsivity of 0.24A/W and an electrical bandwidth of 1.2 GHz for 14.8 V reverse bias at 660 nm. For 520 nm, the N-well/P-substrate PD shows a responsivity of 0.18A/W and an electrical bandwidth of 3.0 GHz for 14.8 V reverse bias.